| 基于FPGA的1553B总线编码解码器的设计 |
| The Design of the Manchester Ⅱ Coders and Decoders for the 1553B Bus Based on FPGA |
| 投稿时间：2006-01-09 修订日期：2006-05-22 |
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| 中文摘要: |
| 介绍用现场可编程逻辑器件(FPGA)设计实现1553B总线接口板中的曼彻斯特码编解码器.该设计采用VHDL硬件描述语言编程,并用专门的综合工具Synplify对设计进行综合、优化,在Modelsim进行时序仿真,最后在FPGA上实现. |
| 英文摘要: |
| This paper discusses the design and realization of the manchester II coders and decoders for the 1553B bus interface card based on FPGA,The design is described by VHDL language and be fitted to the FPGA chips after logic synthesizing based on Synplify and timing simulation based on Modelsim. |
| 李志刚 盖宇 |
| 空军贵阳局,贵州贵阳550025 |
| 中文关键词: 曼彻斯特码 1553B总线 FPGA VHDL |
| 英文关键词:the manchester II coders and decoders,1553B bus,FPGA,VHDL |
| 基金项目: |
| DOI： |
| 引用本文：李志刚,盖宇.基于FPGA的1553B总线编码解码器的设计[J].计测技术,2006,26(4):45~48. |
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